(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to integrate the fabrication of an image sensor cell, and of CMOS logic devices, featuring a non-salicided photodiode element.
(2) Description of Prior Art
Image sensor cells are usually comprised of active image sensing elements, such as photodiodes, in addition to adjacent transistor structures, such as transfer gate transistors, and reset transistors. These transistor structures, as well as additional devices used for the control and signal circuits in the peripheral regions of the image sensor cell, or used for peripheral logic circuits, are comprised with complimentary metal oxide semiconductor, (CMOS), devices. Therefore to reduce process cost and complexity, the image sensor cell has also been fabricated using the same CMOS process sequences used for the peripheral CMOS logic circuits This approach however can influence the quality of the photodiode element, of the image sensor cell, if the photodiode element is subjected to traditional CMOS process sequences. For example if a metal silicide layer is formed on the surface of the photodiode element, during the formation of Self-ALigned metal silICIDE, (Salicide), on the gate structure, as well as on the source/drain region of the CMOS logic circuits, unwanted leakages, in the form of dark current generation, as well as degraded signal to noise, (S/N), ratios, of the image sensor cell, can result.
This invention will describe a process sequence used to form salicide layers on all silicon or polysilicon surfaces of deep submicron CMOS logic devices, (where deep submicron refers to CMOS devices fabricated with channel lengths less than 0.25 .mu.m), in addition to forming salicide on the top surface of a polysilicon gate structure, located in the image sensor cell region, however avoiding salicide formation on the surface of the photodiode element. This selective salicide formation is accomplished without the use of an additional photolithographic masking procedure, using a thin silicon oxide layer to protect the surface of the photodiode element during the salicide formation procedure. A thick organic layer, applied after removal of the thin silicon oxide layer from regions of CMOS logic devices, is etched back allowing only the top surface of a gate structure, located in the image sensor region, to experience the salicide process. This novel process sequence allows the image sensor cell to be formed simultaneously with the high performance logic devices, featuring the desired low dark current generation, and high S/N ratios, as a result of protecting the photodiode element from salicide processing. Prior art, such as Clark et al, in U.S. Pat. No. 5,859,450, describe a process for forming an image sensor cell, but do not use the process sequence described in the present invention to protect the photodiode element from salicide formation. Huang, in U.S. Pat. No. 5,863,820, does describe a fabrication sequence for forming salicide only on elements of logic regions, while protecting regions of memory devices from the same salicide process. However this prior art does not teach the fabrication sequence, detailed in the present invention, in which a thin silicon oxide layer, and a thick organic layer, are patterned to allow salicide formation only on the top surface of a gate structure of an image sensor cell, while protecting the photodiode element of this cell from the same salicide formation procedure.